Search - uart fpga

[VHDL-FPGA-Verilog] uartsample

Description: Xilinx EDK开发通过FPGA实现UART通信-EDK Xilinx development through FPGA to achieve UART communication
Platform: | Size: 2408448 | Author: huowei | Hits:

[VHDL-FPGA-Verilog] Sparten6-CODE-_Verilog

Description: 基于xilinx 厂商的FPGA硬件的开发源代码，包括UART,SPI,以太网通信-The development of FPGA hardware based on xilinx manufacturers source code, including the UART, SPI, Ethernet communication and so on
Platform: | Size: 17125376 | Author: wangxiao | Hits:

[Com Port] Uart_Loop

Description: FPGA串口的模块和一些相关的pdf资料和串口调试助手-uart module for fpga with pdf data
Platform: | Size: 8907776 | Author: terran2831 | Hits:

[Other] S8_UART_V2

Description: 红色飓风开发板提供uart串口程序，verilog实现，一定可以参考并使用-FPGA uart verilog
Platform: | Size: 206848 | Author: wuchun | Hits:

[VHDL-FPGA-Verilog] URAT

Description: 在ISE环境下，用VHDL语言实现RS232串口设计，实现串口通信。通过串口调试工具向 0000000UART发送16进制数，FPGA将UART接收到的串行数据转换为并行数据，并在8个 LED灯上输出显示；同时，并行数据又被重新转换为串行数据，重新送给RS-232接口，并在串口调试工具上再次显示，SW0为复位键。比如：串口调试工具发送两位16进制数，然后能在LED上显示，并且重新在串口调试工具上显示。串口调试工具设置：波特率设为9600，默认奇校验。-In the ISE environment, using VHDL language RS232 serial port design, serial communication. Through the serial debugging tool to 0000000UART Send a hexadecimal number, FPGA serial data received by the UART converted to parallel data, and 8 LED lights on the output display the same time, parallel data has been re-converted to serial data, re-sent to the RS-232 interface, and in Serial debugging tools on the show again, SW0 for the reset button. For example: serial debugging tool to send two 16 hexadecimal number, and then can be displayed on the LED, and re-debugging in the serial port With a display. Serial debugging tool settings: baud rate is set to 9600, the default odd parity.
Platform: | Size: 403456 | Author: panda | Hits:

[VHDL-FPGA-Verilog] uart_test

Description: altra fpga nios 开发uart工程-UART IP and test on nios
Platform: | Size: 13714432 | Author: wangxin | Hits:

[VHDL-FPGA-Verilog] StepperMotor_control_follow

Description: 本源码是基于FPGA来控制步进电机运行上位机发出的精确步数，并能够实时跟踪步进电机行进的位置，通过UART接口与上位机进行串口通信。-The source code is based on FPGA to control the stepper motor running the host computer to send the exact number of steps, and can track the location of the stepper motor in real time, through the UART interface and the host computer for serial communication.
Platform: | Size: 4482048 | Author: Chen | Hits:

[VHDL-FPGA-Verilog] uartfifo

Description: 串口通信例程，使用FIFO数据缓存。Verilog源码，基于FPGA的uart开发，加深理解。-uart communication
Platform: | Size: 256000 | Author: 曹振吉 | Hits:

[VHDL-FPGA-Verilog] UART_Rx_Tx

Description: fpga串口uart，实现fpga与电脑、单片机之间的通信-The fpga uart serial port, realize the fpga and computer, the communication between the SCM (single chip micyoco)
Platform: | Size: 4254720 | Author: 讼淳 | Hits:

[VHDL-FPGA-Verilog] 04_uart_test

Description: 串行通信程序，Verilog示例程序，通用RS232(Serial communication program)
Platform: | Size: 704512 | Author: AIHUI | Hits:

[Other] kehshechenxu

Description: 编制一全双工UART电路，通过试验箱MAX202E转换成RS232电平，与计算机进行通讯实验，设置8个按键，按键值为ASIC码“1”~“8”，通过串口发送给计算机，在计算机上显示键值，同时在数码管最高位显示；计算机可发送“0”~“F”的ASIC码，FPGA接收后在数码管低位显示0~F。通过按键可设置波特率。要求：波特率为三种 1200、2400、9600，由1个按键选择，3个LED分别指示；数据格式为1位起始位、8位数据位和一位停止位；上位计算机发送接收软件可使用“串口调试器“软件；发送和接收数据时，由两个LED分别指示。发挥：自动回发功能、接收到特殊字符（自定义）自动更改波特率。(A full duplex UART circuit, converted into RS232 level by MAX202E test box, communication experiment with computer, set of 8 buttons, keys for ASIC code "1" to "8", to the computer through the serial port to send and display keys on the computer, at the same time in the digital tube display high computer can send "; 0" to "F" in the ASIC code, FPGA after receiving the digital tube display low 0~F. You can set the baud rate by the button. Requirements: baud rate for three, 1200, 2400, 9600, selected by 1 buttons, 3 LED, respectively; The data format consists of 1 bit start bits, 8 bit data bits, and one stop bit; The upper computer sends and receives the software, and the serial debugger can be used; When sending and receiving data, instructions are given by two LED respectively. Play: Auto postback function, receive special characters (custom), change baud rate automatically.)
Platform: | Size: 2948096 | Author: 淡淡的意识 | Hits:

[VHDL-FPGA-Verilog] uart_test

Description: 描述了利用spatran6系列的FPGA，进行串行异步通信的uart串口实现代码(Describes the use of spatran6 series of FPGA, serial asynchronous communication uart serial port to achieve the code)
Platform: | Size: 360448 | Author: cy白菜 | Hits:

[VHDL-FPGA-Verilog] 自己动手写CPU

Description: ? Code文件夹提供了本书每一章涉及的OpenMIPS源代码、测试程序。 ? Tools文件夹提供了GNU工具链的安装文件，以及一个小工具Bin2Mem.exe，该工具用来将二进制数文件转化为可以用于ModelSim仿真的格式。 ? Doc文件夹提供了本书使用的一些IP核的说明手册，包括UART控制器、SDRAM控制器、GPIO模块等。还提供了FPGA开发平台DE2的说明手册。(Code folder Provides the OpenMIPS source code and test program for each chapter of this book. Tools folder Provides an installation file for the GNU tool chain, and a small tool called Bin2Mem.exe that converts binary number files into formats that can be used for ModelSim emulation. Doc folder Some manuals for IP kernel are provided in this book, including UART controller, SDRAM controller, GPIO module and so on. An instruction manual for the FPGA development platform, DE2, is also provided.)
Platform: | Size: 93768704 | Author: 灰太狼的初恋 | Hits:

[Other] UART_source_code

Description: uart verilog code for nexys2 fpga borad
Platform: | Size: 3072 | Author: posljh | Hits:

[SCM] RS232

Description: UART协议实现Verolog源码，可在FPGA上综合(UART Verolog source code)
Platform: | Size: 2048 | Author: Jurge | Hits:

[VHDL-FPGA-Verilog] microblaze实例教程

Description: 一般而言，Xilinx Microblaze会被用来在系统中做一些控制类和简单接口的辅助性工作，比如运行IIC、SPI、UART之类的低速接口驱动，对FPGA逻辑功能模块初始化配置及做些辅助计算等等。类程序的代码量普遍不大，常常在十几KB到几时KB之间，因此对存储的需求通常也不是太高，使用FPGA内部RAM资源便已经够用(Generally speaking, Xilinx Microblaze will be used to do some auxiliary work of control class and simple interface in the system, such as running low-speed interface driver such as IIC, SPI and UART, initializing configuration of FPGA logic function module and doing auxiliary calculation. The amount of code of class programs is generally not large, often between KB and KB, so the demand for storage is usually not too high. The use of FPGA internal RAM resources is enough.)
Platform: | Size: 26932224 | Author: 叮咯咙咚呛36 | Hits:

[VHDL-FPGA-Verilog] 07_uart_test

Description: 黑金FPGA开发板实现串口Uart通信的verilog代码(Serial Uart communication)
Platform: | Size: 390144 | Author: 啊啊啊阿波 | Hits:

[VHDL-FPGA-Verilog] chuankou

Description: UART loopback测试实例，接收PC端发送的UART数据，原数据返回给PC端，即loopback功能可用FPGA开发板验证(The UART loopback test example receives the UART data sent by the PC terminal, and the original data is returned to the PC terminal, that is, the loopback function.)
Platform: | Size: 3581952 | Author: 小猪仔521 | Hits:

[VHDL-FPGA-Verilog] Xilinx_Spartan6 _uart

Description: Xilinx Spartan6 FPGA uart test
Platform: | Size: 1298529 | Author: 570653500@qq.com | Hits:

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[VHDL-FPGA-Verilog] uartsample

[VHDL-FPGA-Verilog] Sparten6-CODE-_Verilog

[Com Port] Uart_Loop

[Other] S8_UART_V2

[VHDL-FPGA-Verilog] URAT

[VHDL-FPGA-Verilog] uart_test

[VHDL-FPGA-Verilog] StepperMotor_control_follow

[VHDL-FPGA-Verilog] uartfifo

[VHDL-FPGA-Verilog] UART_Rx_Tx

[VHDL-FPGA-Verilog] 04_uart_test

[Other] kehshechenxu

[VHDL-FPGA-Verilog] uart_test

[VHDL-FPGA-Verilog] 自己动手写CPU

[Other] UART_source_code

[SCM] RS232

[VHDL-FPGA-Verilog] microblaze实例教程

[VHDL-FPGA-Verilog] 07_uart_test

[VHDL-FPGA-Verilog] chuankou

[VHDL-FPGA-Verilog] Xilinx_Spartan6 _uart

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